1. Field of the Invention
The present invention relates to semiconductor processing, and more particularly relates to high-speed semiconductor transistors and a process for forming same.
2. Description of the Related Art
Improvements in semiconductor technology and semiconductor manufacturing are the main drivers to the reduction of cost and the increase in speed of computers. There have been many improvements to semiconductor devices to increase their speed and performance, ranging from packaging of integrated circuits (xe2x80x9cchipsxe2x80x9d) to the wiring of the devices on the chip, to the design of the devices themselves.
Improvements in chip performance are generally obtained by changing the physical structure of the devices comprising the chip by inventing a new process (or improving an existing process) for making the devices. For example, with the continuing need for smaller integration densities and faster operational speeds, dopant impurity profiles for integrated devices are becoming increasingly shallower with greater dopant concentrations, as compared to previous generations of integrated devices. The shallower dopant profiles and greater dopant concentrations are used to decrease the sheet resistance of-the source and drain regions to obtain faster transient response or logic-state switching rates relative to previous chips.
Thermal annealing techniques, such as rapid thermal annealing (RTA) or rapid thermal process (RTP), are becoming less attractive as options for performing activation annealing of doped regions of an integrated device after dopant implantation. This is mainly because thermal annealing techniques typically require heating the entire substrate to a maximum temperature for a time sufficient to activate the integrated device""s source and drain regions, after which the substrate is permitted to cool to quench the doped source and drain regions. This approach is problematic because the substrate is capable of holding a relatively large amount of thermal energy, which requires significant time to be dissipated via radiation and convection before the dopant ions become incapable of moving due to solidification of the doped regions. Therefore, during the time required for the substrate to cool, the dopant ions can readily move beyond the intended boundaries of the doped regions (a phenomenon which is sometimes referred to as xe2x80x9ctransient enhanced diffusionxe2x80x9d). As a result, the junction depth of the source/drain regions becomes greater than desired. This, in turn, leads to increased off-state leakage currents and thus reduced device performance.
The speed of semiconductor devices has also been limited to date by physical constraints on the amount of activated dopant concentrations. More specifically, for any two species of dopant and substrate ions, under equilibrium conditions, there are only a certain number of dopant ions that can be positioned at activated sites within the crystalline lattice of substrate ions. This limit is known as the xe2x80x98solid solubility limitxe2x80x99. It is generally not possible in the fabrication of semiconductor devices to attain activated dopant concentrations above the solid solubility limit. With thermal annealing techniques, the minimum sheet resistance attainable in the doped regions is controlled by the solid solubility limit, which is 3xc3x971020 ions/cm3 for boron, 2xc3x971021 ions/cm3 for arsenic, and 1.5xc3x971021 ions/cm3 for phosphorous. Lower sheet resistance in the doped regions of an integrated device generally leads to faster transient response or logic-state switching rates. Accordingly, it would be desirable to increase the dopant concentration in active sites within an integrated device""s doped region(s) to levels above the solid solubility limit. Such dopant concentrations are not presently attainable with known conventional annealing techniques.
The nature of the dopant profiles and the carrier concentration affect the performance of the chip. A gradual dopant profile is prone to higher spreading resistance, while a reduced carrier (dopant) concentration can result in a higher sheet resistance than is desired. The formation of abrupt junctions (e.g., sharp dopant profiles) reduces overlap capacitance and spreading resistance, and the ability to increase the dopant concentration lowers the sheet resistance. Both these effects serve to increase the speed and improve the performance of the chip.
There are many prior art semiconductor processes pertaining to improving the performance of a semiconductor device by changing the properties of the device. For example, U.S. Pat. No. 5,756,369 (the ""369 patent), entitled xe2x80x9cRapid thermal processing using narrowband infrared source and feedbackxe2x80x9d, describes rapid thermal processing (RTP) of a semiconductor wafer performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer. However, a shortcoming of this technique is that the temperature of the entire wafer rises to the dopant activation temperature (typically from 800xc2x0 C. to 1100xc2x0 C.). Also, a silicon film is required to be deposited on the backside of the wafer. In addition, a continuous wave CO2 laser is used, which does not allow for sufficient cooling of the wafer region being processed for many applications.
U.S. Pat. No. 5,897,381, (the ""381 patent) entitled xe2x80x9cProcess of forming a layer and semiconductor substratexe2x80x9d, discloses and claims a process of forming a layer on a semiconductor substrate having a front side and a backside, the process comprising the steps of placing a film of material in contact with the backside of the substrate, then directing a beam of narrowband energy onto the film such that the film absorbs the energy and transfers heat to the substrate, then controlling temperatures across the backside of the substrate, and then finally performing an additive process on the front side of the substrate. However, like the ""369 patent, the ""381 patent has the shortcoming that the entire wafer rises to the dopant activation temperature (typically from 800 to 1100xc2x0 C.) when heated. Also, a silicon dioxide film needs to be deposited at the back of the wafer, and a continuous wave CO2 laser is used, which does not allow for sufficient cooling of the wafer region being processed for many applications.
U.S. Pat. No. 5,908,307, entitled xe2x80x9cFabrication process for reduced-dimension FET devicesxe2x80x9d, describes pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth which provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology. However, a shortcoming of this technique is that the polygate may not be able to stand the high laser fluence without appreciable deformation. Another shortcoming is that undesired silicon melting underneath the trench isolation is likely to occur.
U.S. Pat. No. 4,617,066, entitled, xe2x80x9cProcess of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealingxe2x80x9d, describes a process for producing hyperabrupt Pxc2x1 or Nxc2x1 regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant species begins with amorphizing the near-surface layer of a base crystal, and then implanting a steep retrograde distribution of the desired species into the amorphized layer, so that the retrograde distribution lies entirely within the amorphized layer, thereby avoiding channeling effects during implantation. The substantially defect-free structure of the base crystal is restored by annealing the implanted base crystal at a temperature sufficiently high to induce solid phase epitaxial regrowth on the underlying nonamorphized crystal, but at a temperature sufficiently low to avoid significant diffusion of the implanted species. The implanted species is subsequently activated: by a rapid thermal annealing process, at a temperature sufficiently high to activate the implanted species, but for a very short time so that long-range diffusion does not occur. In a preferred embodiment, the implanted species is boron, BF2+, phosphorus, or arsenic in the top 0.20 micrometers of a substantially defect-free silicon base crystal, which may be in a bulk form or epitaxially deposited on an insulator. However, a shortcoming of this technique is that conventional rapid thermal annealing is used, which typically results in diffusion (even over short ranges), which can significantly impact device performance.
U.S. Pat. No. 4,151,008, entitled, xe2x80x9cProcess involving pulsed light processing of semiconductor devices,xe2x80x9d discloses a process in which a pulsed laser or flash lamp produces a short duration pulse of light for thermal processing of selected regions of a semiconductor device. The light pulse is directed towards the semiconductor device and irradiates selected surface regions of the device to be processed. Energy deposited by the light pulse momentarily elevates the temperature of the selected regions above threshold processing temperatures for rapid, effective annealing, sintering or other thermal processing. The characteristics of the light pulse are such that only those surface vicinity regions to be processed are elevated to a high temperature and the remaining mass of the semiconductor device is not subjected to unnecessary or undesirable high temperature exposure. However, a shortcoming of this technique is that the dopant concentration cannot go beyond solid solubility limit.
U.S. Pat. No. 4,456,490, entitled, xe2x80x9cLaser annealing of MIS devices by back surface laser treatment,xe2x80x9d discloses a process for fabricating a metal-insulator-semiconductor integrated circuit, including the step of passing a laser beam through a silicon wafer from the back surface to effect localized heating of an insulating layer, upon which is formed metallic circuit paths. However, a shortcoming of this technique is that the absorbing layer needs to remain as part of the structure of the IC, which is not always desirable.
The present invention relates to semiconductor processing, and more particularly relates to processes of forming an activated doped region in a semiconductor.
A first embodiment of the invention is a process for fabricating a transistor device in a semiconductor substrate having an upper surface, spaced apart shallow trench isolations, and a gate formed on the upper surface between the shallow trench isolations. The process includes the steps of first, forming first amorphous regions in the semiconductor substrate near the upper surface on either side of the gate. The next step is doping the first amorphous regions, thereby forming corresponding first and second doped amorphous extensions. Following the formation of the extensions, the next step is forming side wall spacer structures on either side of the gate. The next step is forming second amorphous regions in the semiconductor substrate adjacent the first and second extensions. The next step is doping the second amorphous regions, thereby forming corresponding doped amorphous deep drain a doped amorphous deep source regions. The next step is forming a strippable conformal layer atop the upper surface of the substrate and the gate. The final step is then performing at least one of front-side irradiation and backside irradiation, thereby providing sufficient heat to the first and second extensions and the deep drain and the deep source regions so as to effectuate activation of the first and second extensions and the deep drain and the deep source regions.
A second embodiment of the invention is also a process for fabricating a transistor device in a semiconductor substrate having an upper surface, spaced apart shallow trench isolations, and a gate formed on the upper surface between the shallow trench isolations. The process according to the second embodiment includes the steps of forming a deep dopant region below the upper surface of the substrate. The next step is then forming first and second amorphous regions in the substrate adjacent the gate and between the upper surface and the deep dopant region. The next step is doping the first and second amorphous regions, thereby forming corresponding first and second extension regions. The next step is then forming second amorphous regions in the semiconductor substrate adjacent the first and second extensions. Following the formation of the extensions, the next step is forming side wall spacer structures on either side of the gate. The next step is then doping the second amorphous regions, thereby forming corresponding doped amorphous deep drain doped amorphous deep source regions respectively having first and second amorphous-crystalline interfaces. The next step is then forming a strippable conformal layer atop the upper surface of the substrate and the gate. Then, the final step is performing at least one of front-side irradiation and backside irradiation, thereby providing sufficient heat to the deep dopant region to effectuate activation of the first and second extensions and the deep drain and the deep source regions.
A third embodiment of the invention is also a process for fabricating a transistor device in a semiconductor substrate having an upper surface, spaced apart shallow trench isolations, and a gate formed on the upper surface between the shallow trench isolations. The process according to the a third embodiment of the invention comprises the steps of first, forming first and second doped extensions the semiconductor substrate near the upper surface on either side of the gate. Following the formation of the extensions, the next step is forming side wall spacer structures on either side of the gate. The next step is then forming doped drain and source regions in the semiconductor substrate adjacent the first and second extensions respectively. The next step is forming a strippable conformal layer atop the upper surface of the substrate and the gate. The final step is then performing at least one of front-side irradiation and backside irradiation, thereby providing sufficient heat to the first and second extensions and the deep drain and the deep source regions so as to effectuate activation of the first and second extensions and the deep drain and the deep source regions.
A fourth embodiment of the invention is a process for fabricating a transistor device in a semiconductor substrate having an upper surface, spaced apart shallow trench isolations, and a gate formed on the upper surface between the shallow trench isolations. The process comprises the steps of first, forming a deep dopant region below the upper surface of the substrate. The next step is then forming first and second doped extensions in the substrate adjacent the gate. Following the formation of the extensions, the next step is forming side wall spacer structures on either side of the gate. The next step is then forming doped deep drain and deep source regions in the substrate between the first and second doped extensions, respectively, and the deep dopant region, the drain and source regions having drain-substrate and source-substrate interfaces, respectively. The next step is then, forming a strippable conformal layer atop the upper surface of the substrate and the gate. The final step is then performing at least one of front-side irradiation and backside irradiation, thereby providing sufficient heat to the deep dopant region to effectuate activation of the first and second extensions and the deep drain and the deep source regions.
Alternate aspects of the above embodiments involve not forming the extensions regions.
In addition, the transistor devices that are formed as a result of the above-described embodiments are further aspects of the present invention.